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Preliminary Technical Data
FEATURES AD5255 Dual, 1024 Position Resolution 10K and 50K Ohm Terminal Resistance Linear or Log taper Settings Increment/Decrement Commands, Push Button Command I2C Compatible 2-Wire Digital Interface +3 to +5V Single Supply Operation 2.5V Dual Supply Operation Nonvolatile Memory Preset 14 bytes of general purpose nonvolatile memory APPLICATIONS Mechanical Potentiometer Replacement Instrumentation: Gain, Offset Adjustment Programmable Voltage to Current Conversion Programmable Filters, Delays, Time Constants Line Impedance Matching Power Supply Adjustment DIP Switch Setting
I2C, Nonvolatile Memory, Dual 1024 Position Digital potentiometers
AD5255
terminal resistance between A-and-B. This linearly changes the wiper to B terminal resistance (RWB) by one position segment of the device's end-to-end resistance (RAB). For non-linear changes in wiper setting a left/right shift command adjusts levels in 6dB steps for sound and light alarm applications. In the direct program mode a predetermined setting of the RDAC register can be loaded directly from the micro controller. The third mode allows the RDAC register to be refreshed with the present nonvolatile data previously stored in the EEMEM register. When changes are made to the RDAC register to establish a new wiper position, the value of the setting can be saved into the EEMEM by executing an EEMEM save operation. Once settings are saved in the EEMEM register, these values will always be transferred to the wiper position (RDAC) register at system power ON by the internal preset strobe and it can be accessed externally as well. The AD5255 is available in the thin TSSOP-16 package. All parts are guaranteed to operate over the extended industrial temperature range of -40C to +85C.
GENERAL DESCRIPTION
The AD5255 is a dual channel, digitally controlled variable resistor (VR) with resolutions of 1024 positions. This device performs the same electronic adjustment function as a potentiometer or variable resistor. The AD5255's versatile programming via a Micro Controller allows multiple modes of operation and adjustment. The basic mode of adjustment is the increment and decrement from the present setting of the Wiper position setting (RDAC) register. An internal scratch pad RDAC register can be moved UP or DOWN, one step of the nominal
FUNCTIONAL BLOCK DIAGRAMS
REV PrB 19 NOV 99 Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106 U.S.A. Tel: 617/329-4700 Fax:617/326-8703
Nonvolatile Memory Digital Potentiometers
VA = +VDD, VB = 0V, -40C < TA < +85C unless otherwise noted.)
AD5255
Min
-1 -2 -30 50 50 200
ELECTRICAL CHARACTERISTICS 25K , 250K OHM VERSIONS (VDD = +3V10% or +5V10% and VSS=0V,
Parameter
Resistor Differential NL2 Resistor Nonlinearity2 Nominal resistor tolerance Resistance Temperature Coefficent Wiper Resistance Wiper Resistance
Symbol
R-DNL R-INL R RAB/T RW RW
Conditions
RWB, VA=NC RWB, VA=NC TA = 25C, VAB = VDD,Wiper (VW) = No connect VAB = VDD, Wiper (VW) = No Connect IW = 1 V/R, VDD = +5V IW = 1 V/R, VDD = +3V
Typ
1
Max
+1 +2 30 100
Units
LSB LSB % ppm/C
DC CHARACTERISTICS RHEOSTAT MODE Specifications apply to all VRs 1/4 1/2
DC CHARACTERISTICS POTENTIOMETER DIVIDER MODE Specifications apply to all VRs Resolution Integral Nonlinearity3 Differential Nonlinearity3 Voltage Divider Temperature Coefficent Full-Scale Error Zero-Scale Error RESISTOR TERMINALS Voltage Range4 Capacitance5 Ax, Bx Capacitance5 Wx Common-mode Leakage Current7 DIGITAL INPUTS & OUTPUTS Input Logic High Input Logic Low Output Logic High Output Logic High Output Logic Low Input Current Input Capacitance5 POWER SUPPLIES Single-Supply Power Range Dual-Supply Power Range Positive Supply Current Programming Mode Current Read Mode Current Negative Supply Current Power Dissipation6 Power Supply Sensitivity DYNAMIC CHARACTERISTICS5, 7 Bandwidth -3dB Total Harmonic Distortion VW Settling Time Resistor Noise Voltage Crosstalk BW_25K THDW tS eN_WB CT R = 10K VA =1Vrms, VB = 0V, f=1KHz VA= VDD, VB=0V, 50% of final value 25K / 250K RWB = 5K, f = 1KHz VA = VDD, VB = 0V, Measue VW with adjacent VR making full scale change 600 0.003 0.6/3/6 9 -65 KHz % s nVHz dB VDD VDD/VSS IDD IDD(PG) IDD(READ) ISS PDISS PSS VSS = 0V VSS = 0V VIH = VDD or VIL = GND VIH = VDD or VIL = GND VIH = VDD or VIL = GND VIH = VDD or VIL = GND, VDD = 2.5V, VSS = -2.5V VIH = VDD or VIL = GND VDD = +5V 10% 2.7 2.2 2 15 650 5.5 2.7 10 V V A mA A A mW %/% VIH VIL VOH VOH VOL IIL CIL with respect to GND with respect to GND RPULL-UP = 2.2K to +5V IOH = 40A, VLOGIC = +5V IOL = 1.6mA, VLOGIC = +5V VIN = 0V or VDD 0.3*VDD 0.7*VDD 4.9 4 0.4 1 5 V V V V V A pF VA,B,W CA,B CW ICM VSS f = 1 MHz, measured to GND, Code = Half-scale f = 1 MHz, measured to GND, Code = Half-scale VA = VB = VDD/2 45 60 0.01 1 VDD V pF pF A N INL DNL VW/T VWFSE VWZSE 10 -2 -1 Code = Half-scale Code = Full-scale Code = Zero-scale -3 0 1/2 1/4 15 -1 +1 +2 +1 +0 +3 Bits LSB LSB ppm/C LSB LSB
10 0.002 0.05 0.01
REV PrB 19 NOV 99 2 Information contained in this Product Concept data sheet describes a product in the early definition stage. There is no guarantee that the information contained here will become a final product in its present form. For latest information contact Walt Heinzer/Analog Devices, Santa Clara, CA. TEL(408)562-7254; FAX (408)727-1550; walt.heinzer@analog.com
Nonvolatile Memory Digital Potentiometers
VA = +VDD, VB = 0V, -40C < TA < +85C unless otherwise noted.)
AD5255
Min 0 1.3 0.6 1.3 0.6 0.6 0 100 Typ1 Max 400 Units KHz s s s s s s ns ns ns s ms ns ns
ELECTRICAL CHARACTERISTICS 25K , 250K OHM VERSIONS (VDD = +3V10% to +5V10% and VSS=0V,
Parameter Symbol fSCL t1 t2 t3 t4 t5 t6 t7 t8 t9 t10 t12 t15 tPR Conditions INTERFACE TIMING CHARACTERISTICS applies to all parts(Notes 5,8) SCL Clock Frequency tBUF Bus free time between STOP & START tHD;STA Hold Time (repeated START) tLOW Low Period of SCL Clock tHIGH High Period of SCL Clock tSU;STA Setup Time For START Condition tHD;DAT Data Hold Time tSU;DAT Data Setup Time tF Fall Time of both SDA & SCL signals tR Rise Time of both SDA & SCL signals tSU;STO Setup time for STOP Condition Store to Nonvolatile EEMEM Save Time9 RDY Rise to CS Fall Preset Pulse Width NOTES:
1. 2. 3. 4 5. 6. 7. 8. 9. Typicals represent average readings at +25C and VDD = +5V. Resistor position nonlinearity error R-INL is the deviation from an ideal value measured between the maximum resistance and the minimum resistance wiper positions. R-DNL measures the relative step change from ideal between successive tap positions. Parts are guaranteed monotonic. See figure 20 test circuit. IW = VDD/R for both VDD=+3V or VDD=+5V. INL and DNL are measured at VW with the RDAC configured as a potentiometer divider similar to a voltage output D/A converter. VA = VDD and VB = 0V. DNL specification limits of 1LSB maximum are Guaranteed Monotonic operating conditions. See Figure 19 test circuit. Resistor terminals A,B,W have no limitations on polarity with respect to each other. Guaranteed by design and not subject to production test. PDISS is calculated from (IDD x VDD=+5V). All dynamic characteristics use VDD = +5V. See timing diagram for location of measured values. All input control voltages are specified with tR=tF=2.5ns(10% to 90% of 3V) and timed from a voltage level of 1.5V. Switching characteristics are measured using both VDD = +3V or +5V. Low only for commands 8, 9,10, 2, 3: CMD_8 ~ 1ms; CMD_9,10 ~0.1ms; CMD_2,3 ~20ms
After this period the first clock pulse is generated
0.9 300 300
0.6 Applies to Command 2H, 3H 50 25
REV PrB 19 NOV 99 3 Information contained in this Product Concept data sheet describes a product in the early definition stage. There is no guarantee that the information contained here will become a final product in its present form. For latest information contact Walt Heinzer/Analog Devices, Santa Clara, CA. TEL(408)562-7254; FAX (408)727-1550; walt.heinzer@analog.com
Nonvolatile Memory Digital Potentiometers
Timing Diagram
t8
AD5255
SDA
t1 t8 t9 t6
SCL
t2 t3
P S
t4
t5
Sr
t7
P
t10
Figure 1. Timing Diagram Data of AD5255 is accepted from the I2C bus in the following serial format: S 0 1 0 1 1 A A R/ A I7 I6 I5 I4 I3 I2 I1 I0 A X X X X X D D D A D D D D D D D D A P 198 76543210 D DW 10 Slave Address Byte Where: S = Start Condition P = Stop Condition A = Acknowledge X = Don't Care Instruction Byte 0 Data Byte 1 Data Byte 0
AD1, AD0 = Package pin programmable address bits R/W= Read Enable at High and Write Enable at Low I7 - I1 = Instruction bits O2, O1 = Output logic pin latched values D9 - D0 = 10 Data Bits
SLAVE ADDRESSAND R/WBYTE
INSTRUCTIONBYTE
D ATA BYTE 1
DATA BYTE 0
SDA
AD6 MSB
AD5
AD0
R/W LSB ACK
A/B MSB
AM0
RS
SD LSB ACK
D9 MSB
D8
D3
D2 LSB ACK
D1 MSB
D0
X
X LSB ACK
SCL
START Condition STOP Condition
Figure 2.Complete Serial Transmission
REV PrB 19 NOV 99 4 Information contained in this Product Concept data sheet describes a product in the early definition stage. There is no guarantee that the information contained here will become a final product in its present form. For latest information contact Walt Heinzer/Analog Devices, Santa Clara, CA. TEL(408)562-7254; FAX (408)727-1550; walt.heinzer@analog.com
Nonvolatile Memory Digital Potentiometers
Absolute Maximum Rating (TA = +25C, unless otherwise noted) VDD to GND...........................................................-0.3, +7V VSS to GND .............................................................. 0V, -7V VDD to VSS ......................................................................+7V VA, VB, VW to GND............................................... VSS, VDD AX - BX, AX - WX, BX - WX .................................... 20mA Digital Inputs & Output Voltage to GND ................. 0V, +7V Operating Temperature Range .......................-40C to +85C Maximum Junction Temperature (TJ MAX) .................+150C Storage Temperature....................................-65C to +150C Lead Temperature (Soldering, 10 sec)........................+300C Thermal Resistance JA, TSSOP-16................................................... 180C/W
Package Power Dissipation = (TJMAX - TA) / JA
SCL SDA AD0 GND VSS A1 W1 B1 1 2 3 4 5 6 7 8 16 RDY 15 AD1 14 PR 13 WP 12 VDD 11 A2 10 W2 9 B2
AD5255
AD5255 PIN CONFIGURATION
AD5255 PIN FUNCTION DESCRIPTION # Name Description
1 2 3 SCL SDA AD0 Serial Clock Input Serial Address & Data Input/Output Programmable address input 0 for multiple package decoding. Bits AD0 and AD1 provide 4 possible addresses. Ground pin, logic ground reference Negative Supply. Connect to zero volts for single supply applications. A terminal of RDAC1. Wiper terminal of RDAC1, ADDR(RDAC1) = 0H. B terminal of RDAC1. B terminal of RDAC2. Wiper terminal of RDAC2, ADDR(RDAC2) = 1H. A terminal of RDAC2. Positive Power Supply Pin. Should be the input-logic HIGH voltage. Write Protect Pin. Prevents any changes to the present EEMEM contents when active low. Hardware over ride preset pin. Refreshes the scratch pad register at active low with current contents of the EEMEM register. Factory default loads midscale 51210. Programmable address input 1 for multiple package decoding. Bits AD0 and AD1 provide 4 possible addresses. Ready. Active-high open drain output. Identifies completion of commands 2, 3, 8, 9, 10.
Ordering Guide
Model
AD5255BRU25
#CHs/ k Ohm
X2/25
Temp Range
Package Package Description Option
RU-16 RU-16
-40/+85C TSSOP-16 -40/+85C TSSOP-16
4 5
GND VSS A1 W1 B1 B2 W2 A2 VDD
AD5255BRU250 X2/250
The AD5255 contains x,xxx transistors. Die size: x' mil x y' mil, z' sq. mil
6 7 8 9 10 11 12 13 14
WP PR
15
AD1
16
RDY
REV PrB 19 NOV 99 5 Information contained in this Product Concept data sheet describes a product in the early definition stage. There is no guarantee that the information contained here will become a final product in its present form. For latest information contact Walt Heinzer/Analog Devices, Santa Clara, CA. TEL(408)562-7254; FAX (408)727-1550; walt.heinzer@analog.com
Nonvolatile Memory Digital Potentiometers
OPERATIONAL OVERVIEW
The AD5255 digital potentiometer is designed to operate as a true variable resistor replacement device for analog signals that remain within the terminal voltage range of VSSAD5255 employs a two-wire I2C serial interface requiring only two I/O lines of a standard microprocessor port. Key features of this interface include: * Read & Write capability to all registers * Direct parallel refresh of all RDAC wiper registers from mirrored EEMEM registers * Increment & Decrement instructions for each RDAC wiper register * Left & right Bit Shift of all RDAC wiper registers to achieve 6dB level changes * Permanent storage of the present scratch pad RDAC register values into the mirrored EEMEM register * 32 bits of user addressable electrical-erasable memory Figure 1 shows the timing diagram for signals on the wire bus. The 2-wire bus can have several devices attached in addition to the AD5255. The two bus lines (SDA and SCL) must be high when the bus is not in use. When in use, the port bits are toggled to generate the appropriate signals for SDA and SCL. For I2C applications, two pull up resistors are required at both the SDA and SCL pins to VDD. The AD5255 can operate SCL of up to 400KHz. A master device sends information to the AD5255 by transmitting the AD5255's address over the bus and then transmitting the desired information. Each transmission consists of a START condition, the AD5255's programmable slave address, an instruction byte, 2 data bytes consist of 10 data bits, and a STOP condition.
AD5255
The address byte, instruction byte, and data bytes are transmitted between the START and STOP conditions. The state of SDA is allowed to change only if SCL is low, with the exceptions at START and STOP conditions. SDA must remain stable and is sampled ( read or write depends upon the state of R/W) when SCL is high. Data is transmitted in 8-bit bytes. The START and STOP Conditions When the bus is not in use, both SCL and SDA must be high. A bus master signals the beginning of a transmission with a START condition by transitioning SDA from high to low while SCL is high (Figure 3). When the master has finished communicating with the slave, it issues a STOP condition by transitioning SDA from low to high while SCL is high. The bus is then free for another transmission.
SDA
SCL
START Condition STOP Condition
Figure 3.START and STOP Conditions The Slave Address The AD5255's slave address is seven bits long (Figure 4). The first five bits (MSBs) of the slave address have been factory programmed to 01011. The state of the AD5255 inputs AD0 and AD1 determine the final two bits of the 7-bit slave address, These input pins may be connected to VDD or GND, or may be actively driven by TTL or CMOS logic levels. There are four possible addresses for the AD5255, and therefore a maximum of four such devices may be on the bus at the same time. The eighth bit (LSB) in the slave address byte is for read write purpose. Active high allows data to be read back from the input register. Active low allows data to be written to the input register. The AD5255 watches the bus continuously, waiting for a START condition followed by its slave address. When it recognizes its slave address, it is ready to accept data.
SLAVE ADDRESSANDR/WBYTE
SDA
0 MSB
1
0
1
1
AD1
AD0
R/W LSB ACK
SCL
Figure 4. Slave Address and R/W Byte The Instruction Byte ..................... The Data Bytes .....................
REV PrB 19 NOV 99 6 Information contained in this Product Concept data sheet describes a product in the early definition stage. There is no guarantee that the information contained here will become a final product in its present form. For latest information contact Walt Heinzer/Analog Devices, Santa Clara, CA. TEL(408)562-7254; FAX (408)727-1550; walt.heinzer@analog.com
Nonvolatile Memory Digital Potentiometers
Table 1. AD5255 Instruction/Operation Truth Table
Slave Address & R/W Byte B31 ........................................ B24 AD6 AD5 AD4 AD3 AD2 AD1 AD0 R/W 0 101 1 00 0 0 101 1 00 1 0 101 1 00 0 0 101 1 00 1 0 101 1 00 0 0 101 1 00 1 0 101 1 00 0 0 101 1 00 1 0 101 1 00 0 0 101 1 00 1 0 101 1 00 0 0 101 1 00 1 0 101 1 00 0 0 101 1 00 1 0 101 1 00 0 0 101 1 00 1 Instruction Byte B23 ....................................... B16 I7 I6 I5 I4 I3 I2 I1 I0 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 Data Byte 1 B15 ...... B8 X ......... D8 X ......... X X ......... X X ......... X X ......... X X ......... X X ......... X X ......... X X ......... X X ......... X X ......... X X ......... X X ......... X X ......... X X ......... X X ......... X X ......... X Data Byte 0 B7 ......... B0 D7 ......... D0 X ........... X X ........... X X ........... X X ........... X X ........... X X ........... X X ........... X X ........... X X ........... X X ........... X X ........... X X ........... X X ........... X X ........... X X ........... X X ........... X Operation
AD5255
NOTES: 1. The RDAC register is a volatile scratch pad register that is refreshed at power ON from the corresponding non-volatile EEMEM register. 2. The increment, decrement and shift commands ignore the contents of the shift register Data Byte 0.
REV PrB 19 NOV 99 7 Information contained in this Product Concept data sheet describes a product in the early definition stage. There is no guarantee that the information contained here will become a final product in its present form. For latest information contact Walt Heinzer/Analog Devices, Santa Clara, CA. TEL(408)562-7254; FAX (408)727-1550; walt.heinzer@analog.com
Nonvolatile Memory Digital Potentiometers
Latched Digital Outputs A pair of digital outputs, O1 & O2, are available in the AD5255 and it provides a nonvolatile logic 0 or logic 1 setting. O1 & O2 are standard CMOS logic outputs shown in figure 5. These outputs are ideal to replace functions often provided by DIP switches. In addition, they can be used to drive other standard CMOS logic controlled parts that need an occasional setting change.
VDD OUTPUTS O1 & O2 PINS
AD5255
Figure 6. Equivalent RDAC structure
PROGRAMMING THE VARIABLE RESISTOR Rheostat Operation The nominal resistance of the RDAC between terminals A and B are available with values of 10K and 50K. The final digits of the part number determine the nominal resistance value, e.g., 10K = 10 and 50K = 50. The nominal resistance (RAB) of the AD5255 VR has 1024 contact points accessed by the wiper terminal, plus the B terminal contact. The 10-bit data word in the RDAC latch is decoded to select one of the 1024 possible settings. The wiper's first connection starts at the B terminal for data 00H. This B-terminal connection has a wiper contact resistance of 50. The second connection (10K part) is the first tap point located at 60 [=RAB(nominal resistance)/1024 + RW = 10+50)] for data 01H. The third connection is the next tap point representing 20+50= 70 for data 02H. Each LSB data value increase moves the wiper up the resistor ladder until the last tap point is reached at 10040. The wiper does not directly connect to the B terminal. See figure 6 for a simplified diagram of the equivalent RDAC circuit. The general transfer equation, which determines the digitally programmed output resistance between Wx and Bx, is: RWB(Dx) = (Dx)/2N*RAB + RW eqn. 1
GND
Figure 5. Logic Outputs O1 & O2. Detail Potentiometer Operation The actual structure of the RDAC is designed to emulate the performance of a mechanical potentiometer. The RDAC contains a string of connected resistor segments, with an array of analog switches that act as the wiper connection to several points along the resistor array. The number of points is the resolution of the device. For example, the AD5255 emulates 1024 connection points with 1024 equal resistance, Rs, allowing it to provide better than 0.5% set-ability resolution. Figure 6 provides an equivalent diagram of the connections between the three terminals that make up one channel of the RDAC. The switches SWA and SWB will always be ON while one of the switches SW(0) to SW(2N-1) will be ON one at a time depends upon the resistance step decoded from the data. The total resistance of the active switches makes up the wipe resistance, RW.
SW A
Where N is the resolution of the VR, Dx is the data contained in the RDACx latch, and RAB is the nominal end-to-end resistance. For example, when VB = 0V and A-terminal is open circuit, the following output resistance values will be set by the corresponding RDAC latch codes (applies to the 10-bit, 10K potentiometers): D (DEC) RWB () 10040 5050 60 50 Output State
AX
RS
SW(2 -1) RDAC WIPER REGISTER & DECODER
N
RS
SW(2 N-2)
WX
1023 512 1 0
Full-Scale Mid-Scale 1 LSB Zero-Scale (Wiper contact resistance)
RS
SW(1)
RS
SW(0)
Note that in the zero-scale condition a finite wiper resistance of 50 is present. Care should be taken to limit the current flow between W and B in this state to a maximum value of 5mA to avoid degradation or possible destruction of the internal switch contact.
RS = R AB / N DIGITAL CIRCUITRY OMITTED FOR CLARITY
SW B
BX
REV PrB 19 NOV 99 8 Information contained in this Product Concept data sheet describes a product in the early definition stage. There is no guarantee that the information contained here will become a final product in its present form. For latest information contact Walt Heinzer/Analog Devices, Santa Clara, CA. TEL(408)562-7254; FAX (408)727-1550; walt.heinzer@analog.com
Nonvolatile Memory Digital Potentiometers
AD5255
any value starting at zero volts up to 1 LSB less than +5V. Each LSB of voltage is equal to the voltage applied across terminal AB divided by the 2N position resolution of the potentiometer divider. The general equation defining the output voltage with respect to ground for any given input voltage applied to terminals AB is: VW(Dx) = Dx/2N * VAB + VB Operation of the digital potentiometer in the divider mode results in more accurate operation over temperature. Here the output voltage is dependent on the ratio of the internal resistors and not the absolute value; therefore, the drift reduces to 15ppm/C. Figure 7. Symmetrical RDAC Operation ESD PROTECTION CIRCUITS Like the mechanical potentiometer the RDAC replaces, the AD5255 part is totally symmetrical. The resistance between the wiper W and terminal A also produces a digitally controlled resistance RWA. Figure 7 shows the symmetrical programmability of the various terminal connections. When these terminals are used the B-terminal should be tied to the wiper. Setting the resistance value for RWA starts at a maximum value of resistance and decreases as the data loaded in the latch is increased in value. The general transfer equation for this operation is: RWA(Dx) = (2N-Dx)/2N*RAB + RW eqn. 2
VDD OUTPUTS O1 & O2 PINS
VDD
INPUTS LOGIC PINS
GND
Figure 8A. Equivalent Digital Input ESD Protection where N is the resolution of the VR, Dx is the data contained in the RDACx latch, and RAB is the nominal end-to-end resistance. For example, when VA = 0V and B-terminal is tied to the wiper W the following output resistance values will be set by the corresponding RDAC latch codes (applies to 10-bit, 10K potentiometers): D (DEC) 1023 128 1 0 RWA () 60 5050 10040 10050 Output State
Full-Scale Mid-Scale 1 LSB Zero-Scale
GND
Figure 8B. Equivalent Digital Output ESD Protection
The typical distribution of RAB from channel-to-channel matches within 1%. However device to device matching is process lot dependent having a 30% variation. The change in RAB with temperature has a 50 ppm/C temperature coefficient. PROGRAMMING THE POTENTIOMETER DIVIDER Voltage Output Operation The digital potentiometer easily generates an output voltage proportional to the input voltage applied to a given terminal. For example connecting A-terminal to +5V and B-terminal to ground produces an output voltage at the wiper which can be
Figure 8 shows the equivalent ESD protection circuit for digital pins. Figure 9 shows the equivalent analog-terminal protection circuit for the variable resistors.
REV PrB 19 NOV 99 9 Information contained in this Product Concept data sheet describes a product in the early definition stage. There is no guarantee that the information contained here will become a final product in its present form. For latest information contact Walt Heinzer/Analog Devices, Santa Clara, CA. TEL(408)562-7254; FAX (408)727-1550; walt.heinzer@analog.com
Nonvolatile Memory Digital Potentiometers
POTENTIOMETER TERMINALS A, B, W PINS
AD5255
Figure 14. Inverting Gain test Circuit
VSS
Figure 9. Equivalent VR-Terminal ESD Protection TEST CIRCUITS Figures 10 to 15 define the test conditions used in the product specification's table. Figure 15. Non-Inverting Gain test circuit
Figure 10. Potentiometer Divider Nonlinearity error test circuit (INL, DNL)
Figure 16. Gain Vs Frequency test circuit
Figure 11. Resistor Position Nonlinearity Error (Rheostat Operation; R-INL, R-DNL) Figure 17. Incremental ON Resistance Test Circuit
Figure 12. Wiper Resistance test Circuit Figure 18. Common Mode Leakage current test circuit TYPICAL PERFORMANCE GRAPHS TBD
Figure 13. Power supply sensitivity test circuit (PSS, PSSR)
REV PrB 19 NOV 99 10 Information contained in this Product Concept data sheet describes a product in the early definition stage. There is no guarantee that the information contained here will become a final product in its present form. For latest information contact Walt Heinzer/Analog Devices, Santa Clara, CA. TEL(408)562-7254; FAX (408)727-1550; walt.heinzer@analog.com
Nonvolatile Memory Digital Potentiometers
OUTLINE DIMENSIONS
Dimensions shown in inches and (mm)
AD5255
REV PrB 19 NOV 99 11 Information contained in this Product Concept data sheet describes a product in the early definition stage. There is no guarantee that the information contained here will become a final product in its present form. For latest information contact Walt Heinzer/Analog Devices, Santa Clara, CA. TEL(408)562-7254; FAX (408)727-1550; walt.heinzer@analog.com

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